| 产品号 | 产品描述 | 封装形式 |
| SICGD01 | Four-Output PCIe/Gen1/Gen2/Gen3/Gen4 Clock Buffer and Level Translator | QFN |
| SICGD02 | 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family | SSOP |
| SICGD03 | 3.3-V Clock Phase-Lock Loop Clock Driver, output frequency up to 250MHz | SSOP |
| SICGD04 | Four-Output LVDS Buffer, frequency up to 800MHz | QFN |
| SICGD05 | 2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER, SSTL output, JEDEC Standard (JESD82-1/1A) | SSOP |
| SICGD06 | Configurable registered buffer, Support SSTL input and output | QFN |
| SICGD07 | Low phase noise buffer/driver, LVPECL, LVDS, CMOS output | QFN |
| SICGD08 | Programmable Low Voltage 1:10 LVDS clock driver, signaling rate up to 1.2GHz | QFP |
| SICGD09 | 1.8 V, 12-LVDS(1.2GHz)/24-CMOS(250MHz) Output clock buffer | QFN |
| SICGD10 | Silicon oscillator 10MHz, initial accuracy +/-3% | SSOP |
| SICGD11 | Silicon oscillator 100MHz, initial accuracy +/-3% | SSOP |
| SICGD12 | 1.6 GHz to 2.5 GHz Receiver Front End | QFN |
| SICGD13 | Digital phase frequency detector, rate up to 1.2GHz | QFN |
| SICGD14 | 2 GHz low noise programmable divider (N = 1 to 64) | QFN |
| SIcCGD15 | 3-GHz 10-Output Differential Clock Buffer/Level Translator (LVPECL, LVDS, CML, SSTL,HSTL, HCSL, or CMOS) | QFN |
| SIcCGD16 | Dual Clock Divider Buffer, rate up to 3GHz, 8 differential output, N=1 to 512 | QFN |
| SIcCGD17 | 6GHz 12 Ouput CML Buffer | QFN |
| SIcCGD18 | 0 – 4GHz Programmable frequency divider | QFN |